A picture of Raimund Kirner

Raimund Kirner

  • Job Title:
    • Reader in Cyberphysical Systems
  • Office Hours:
    • by appointment
  • Location:
    • room LB205

I am Reader in Cyberphysical Systems at the Compiler Technology and Computer Architecure Group at the University of Hertfordshire.

In addition, I am Adjunct Professor (Habilitation) at the Institute of Computer Engineering, Cyber-Physical Systems Group at the Vienna University of Technology.

I have studied computer science at the Vienna University of Technology, obtaining a Dipl.-Ing. (Master's) degree in 2000 and a Dr.techn. (PhD) degree in 2003. Before my academic career I also spent several years in industry, in particular in the field of high frequency engineering and embedded software development. This diversified experience makes me a strong believer of the mutual enrichment of the industrial and academic point of view when brought together. As a consequence I like the inspiration of my research by practical problems, aiming to build up rigorous concepts on top of it to find insights about feasibility and practical solutions.

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My research broadly covers development methodologies for cyber-physical systems, i.e., networked embedded sysstems. My research is based on real-world problems and I enjoy the ability to contribute to the technical state-of-the-art.

In particular, my research interests include the following topics:

Cyber-physical Systems Design
Cyber-physical systems (CPS) are networked embedded systems. CPS include the following design aspects: We work on modelling techniques to describe CPS in structured ways to provide locality of system behaviour. We also work on the specification and assurance of extra-functional properties for CPS, including timing semantics and reliability. We also work on resource management of runtime systems for CPS.
Parallel Computing
Parallel computing offers the challenge that the individual jobs executing in parallel may influence each other, for example, with regards of extra-functional properties like execution time. Adequate hardware and software architectures are necessary to bridge the gap between the many-core computing and embedded computing. Further, many-core computing also offers to be the base for novel approaches of robust computing.
In collaboration with Alex Shafarenko I am the local coordinator at UH of the FP7 project ADVANCE, where the goal is to use of probabilistic runtime information to optimize S-Net programs. This includes program transformations and resource management like load balancing. Since 2012 I am the principal investigator at UH of the ARTMIS project CRAFTERS, where the goal is to develop multi-core systems, including predictability and reliability.
Worst-Case Execution Time Analysis
The worst-case execution time (WCET) of a program is the maximum execution time it can take on a concrete target hardware. The knowledge of the WCET of tasks is crucial for the design of real-time systems. Only if safe upper bounds for the WCET of all time-critical tasks have been established, it becomes possible to verify the timeliness of the whole real-time system.
Im am the principal investigator of the FORTAS-rt project, funded by the FWF. In cooperation with the research group of Prof. Helmut Veith, the reseach of FORTAS-rt focues on measurement-based timing analysis using efficient automatic generation of test-data.
Compiler Support for WCET Analysis
Due to complexity limits and only partially available system descriptions during the analysis, the calculation of the WCET requires the provision of additional control flow information (flow information). For convenience of the developers the flow facts have to be provided at source-code level. But the WCET analysis has to be performed at object-code level to obtain tight results. Therefore, it is necessary by the compiler to transform the flow information from source-code to object-code level. The flow information has to be transformed in case of control-flow changing code optimizations performed by the compiler.
I have been principal investigator of the CoSTA project, funded by the FWF. The research in CoSTA focuses on the generation of predictable code patterns on processors with timing anomalies and on the transformation of flow information from source code to object code.
Predictable Computer Architectures
WCET analysis is quite complex on modern computer systems. Modern processors that contains features like pipelines or caches maintain an internal state to improve peak performance. Modelling this internal state exactly to calculate a tight WCET value is often infeasible. The infeasibility comes from the state explosion due to input-data-dependent control flow and cache states. The development of more predictable software and hardware concepts will reduce the complexity of WCET analysis. Specific programming paradigms can help to reduce the complexity of control-flow path analysis.
Verification of Embedded Systems
Systematic testing is becoming increasingly important in the development of embedded systems. Within our research we focus on techniques to automate the generation of test cases using formal techniques like model checking.
I have been the local coordinator together with Peter Puschner of the TeDES project at the Vienna University of Technology. Within TeDES, a functional testing framework with automatic test case generation has been developed.
I have been the principal investigator of the SECCO project, funded by the FWF. With the SECCO project we initiated the novel field of research on preserving structural code coverage during code optimization. Systematic generation of test data at source-code level is especially useful for embeddedd computing, where portability of development and verification frameworks is of high importance. With the work in SECCO we enable code optimization during compilation while still preserving the structural code coverage initially achieved by a systematic test-data generation framework at source-code level. A prototype implementation based on the GCC compiler has shown that coverage preservation can be achieved at negligible performance costs, meaning that additional safety and performance are not contradicting goals.
Decidability Issues: Did you know that the Halting Problem is decidable for ISO C programs but not for Java programs, while for JAVA bytecode programs it still is? The following article does explain it: On Undecidability Results of Real Programming Languages.

Presentations available online:

Raimund Kirner is a member of the IEEE Computer Society, the ACM, and the Austrian Computer Society (OCG).


Publications and research reports are described in the publication page.


Teaching at UH, 2016/17:

Teaching at UH, 2015/16:

Teaching at UH, 2014/15:

Teaching at UH, 2013/14:

Teaching at UH, 2012/13:

I supervise a number of PhD students at University of Hertfordshire. You may contact me if you have excellent crendentials and you are interested in the subject of my research.


RTJava: Development of Real-Time JAVA Virtual Machine (2013-2016)
Funding: this Knowledge Transfer Partnership (KTP) is funded by the Innovate UK (acquired funding: € 202k).
Role: Principal Investigator
The goal of the project is to develop a Java virtual machine supporting real-time computing according to the Real-Time Specification for Java, suitable for hosting future satellite terminals based on Software Defined Radio (SDR). High portability to new hardware is an utmost requirement of the virtual machine.

TACLe: Timing Analysis on Code-Level (2012 - 2015)
Funding: this ICT Cost Action is funded by the EC under contract IC1202.
Role: Principal Investigator at HERTS
The focus of this COST action is to enable the networking of the different European research groups working on worst-case execution time (WCET) analysis and time-predictable computing.

CRAFTERS: ConstRaint and Application driven Framework for Tailoring Embedded Real-time Systems (2012 - 2015)
Funding: ARTEMIS-JU (EC and UK-funding by Innovate UK) (in total: € 3106k, aquired funding at local institution: € 710k)
Role: Lead of Subproject 3 (10 partners) and Principal Investigator at HERTS
The goal of this project is to develop a multi-core platform for the embedded domain including a tool chain for software development and analysis. At HERTS we extend a coordination language with robustness measures to enable compiler-supported fault tolerance.

Finished projects

ADVANCE: Virtualization through performance ANalysis to support Concurrency Engineering (2010 - 2013)
Funding: FP7 strep (EC) (at local institution: € 785k)
Role: Principal Investigator at HERTS (with Alex Shafarenko as Project Coordinator)
The goal of the project is to develop statistical feedback-based software optimisation techniques for parallel programs.

FORTAS-RT: Formal Timing Analysis Suite of Real-Time Systems (2007 - 2011)
Funding: the project has been funded by the Austrian Fonds zur Foerderung der wissenschaftlichen Forschung (FWF) under contract No P19230-N13 (aquired funding: € 273k).
Role: Principal Investigator
The focus of the project was to develop a measurement-based timing analysis framework with efficient formal methods to automatically abstract the program model, to generate test data, and to refine the model.

SECCO: Sustaining Entire Code-Coverage on Code Optimization (2008 - 2010)
Funding: the project has been funded by the Austrian Fonds zur Foerderung der wissenschaftlichen Forschung (FWF) under contract No P20944-N13 (aquired funding: € 130k).
Role: Principal Investigator
The focus of the project was to develop a compilation profile for optimizing compilers to ensure code coverage at machine code with test date that achieve code coverage at source code.

CoSTA: Compiler-Support for Timing Analysis (2006 - 2009)
Funding: the project has been funded by the Austrian Fonds zur Foerderung der wissenschaftlichen Forschung (FWF) under contract No P8925-N13 (aquired funding: € 263k).
Role: Principal Investigator
The focus of the projet was to extend compilation technology in order to simplify worst-case execution time (WCET) analysis.

TeDES: Systematic Test Case Generation for Safety-Critical Distributed Embedded Real-Time Systems with Different SIL Levels (2005 - 2007)
Funding: the project has been funded by the Austrian ministry for transport, innovation, and technology (BM-VIT) under contract No 809446/2297 within the FIT-IT program.
Role: Principal Co-Investigator at TU Vienna (together with Peter Puschner)
The focus of the project was to develop a testing framework with systematic generation of test data.

MoDECS: Model-Based development of Distributed Embedded Control Systems (2003 - 2005)
Funding: the project has been funded by the Austrian ministry for transport, innovation, and technology (BM-VIT) under contract No 807144 within the FIT-IT program.
Role: Senior Researcher
The focus of the project was to develop a time-predictable software development method, where TU Vienna developed a measurement-based (called hybrid) timing analysis framework with automatic systematic test-data generation.

SETTA: Systems Engineering of Time-Triggered Architectures (2000 - 2001)
Funding: the project has been funded by the European Commission under contract No IST-10043 within the FP-5 Information Society Technologies programme.
Role: Researcher
The focus of the project was to build a conforming software delopment process for the automotive domain based on time-triggered technology (Flexray). Within the project I developed a static worst-case execution time analysis tool - called CalcWCET167 - for the Infineon C167 processor.




Cycling in the UK

Do you live in the UK and consider to do something good for your health by cycling to your work place? Then you might be interested in the UK Cycle Scheme to get a voucher for your bicycle.

Writing Scientific Papers in LaTeX

Are you considering to get started with writing scientific papers in LaTeX? Then this guide might help you: pdf (LaTeX sources). As the report was written in 2007, the tools sections is a bit outdated. For example, I would nowadays recommend to try out TexStudio as a LaTeX writing environment, which is available for multiple platforms.


Uncertain about your career?
If you tend to pursue an academic career, please have a look at the PHD Comics to decide whether this is yours.
If you are interested in an industrial career, please have a look at Dilbert Comics to see what you are striving for.

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This page was last updated on April 5th 2010 by r.kirner (@) herts.ac.uk